1. Field of the Invention
The invention relates to a flip-flop for storing logic state information in a circuit block, which retains the state information when the flip-flop and the surrounding circuit block are turned off.
2. Description of the Related Art
In order to reduce the power loss of a system, it is known to turn off circuit blocks, in particular logic blocks, which are temporarily not required for the function of the system. In general, the respective circuit block is turned off by decoupling the circuit block from the supply voltage. In order to isolate the respective circuit block from the negative pole (VSS; e.g. 0 V) of the supply voltage, a large N-MOS transistor (N-MOS power switch) is used, which is arranged between the VSS node and the block-internal supply terminal (VVSS—virtual VSS). As an alternative, the respective circuit block can be isolated from the positive pole (VDD; e.g. 1.2 V) of the supply voltage, a large P-MOS transistor (P-MOS power switch) being used in this case, which is connected between the VDD node and the block-internal supply terminal (VVDD—virtual VDD). The prior art also describes combined methods which use both P-MOS and N-MOS power switches within the same circuit block. The block-internal supply potentials VVDD and VVSS are also referred to as virtual supply potentials. Turning off circuit blocks in this way is known in the prior art by the terms “Multiple Threshold CMOS” (MTCMOS), “Circuit Block Switch-off” (CB-SO) or “Sleep Transistor Technique”.
If an N-MOS or P-MOS power switch, which is also referred to as “Cut Off Transistor”, “Sleep Transistor”, “Footer” or “Header” in the prior art, is turned off, the leakage currents charge the internal capacitances until the potential of all the signal nodes within the turned-off circuit block and the potential of the block-internal VVSS or VVDD node has reached a value near the potential of the non-connected pole of the supply voltage (i.e. VDD or VSS). The voltage across the switched-off circuit block collapses in this way.
What is disadvantageous about the turn-off of a circuit block is that circuit parts situated within the circuit block that effect storage, such as, for example, flip-flops, memory cells or memory arrays, lose their storage content after the turn-off. At the system level, therefore, it is necessary to decide whether these storage contents are irrelevant and their loss due to the turn-off can be accepted, or whether the storage contents and thus the state of the relevant circuit block must be maintained. In the latter case, the corresponding storage contents can be swapped into a block-external memory that is not turned off, for example an SRAM (static random access memory). As an alternative, special flip-flops whose storage state is not lost due to the turn-off may be used within the circuit block to be turned off. Flip-flops of this type are also referred to as state retention flip-flops. The use of state retention flip-flops is preferable to a SRAM-based solution since the latter is associated with a significantly increased power loss consumption and a latency for swapping and loading the storage contents.
Various forms of implementation of state retention flip-flops are described in the documents “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS”, Mutoh et al., IEEE JSSC, Vol. 30., No. 8., August 1995; U.S. Pat. No. 5,473,571; US 2003/0188241 and US 2004/051574. These forms of implementation of a state retention flip-flop that are known from the prior art are based on the use of an additional latch stage for storing the data in the event of the circuit block being turned off, which is situated either in the data path of the flip-flop or in a path in parallel therewith. This additional latch stage is also referred to as “Shadow Latch” or “Balloon Latch”. In the case of a shadow latch of this type, so-called thick oxide MOS transistors (that is to say with a thick oxide for reducing the gate tunelling current) in conjunction with a high threshold voltage are used for reducing the leakage currents. When the voltage supply of the circuit block is turned off, the voltage supply of the shadow latch is maintained. For this purpose, the shadow latch is connected to the VDD node instead of the VVDD node or to the VSS node instead of the VVSS node.
What is disadvantageous about forms of implementation of a state retention flip-flop that are known from the prior art is that such state retention flip-flops within a circuit block have to be supplied not with two supply potentials but rather with at least three supply potentials, namely with the virtual supply potential VVDD or VVSS and the two non-connected supply potentials VDD and VSS. In a full custom design, the outlay for this can be handled, in principle, by means of skilful positioning of the flip-flops. By contrast, the additional outlay on account of the third supply potential is considerable in the case of an automatic, computer-aided circuit block synthesis by means of a so-called place-and-route tool. In order to supply the shadow latch stages with the additional supply potential, it is necessary in this case generally to provide an additional, third supply rail in the layout of all the standard cells of a circuit block that can be turned off, said third supply rail leading through all the standard cells. FIG. 1 shows by way of example a standard cell of this type, having besides a VDD rail and a VVSS rail in addition a VSS rail as third supply rail for supplying the shadow latch stage. In view of the limited number of metallization planes, considerable limitations for the remaining wiring result on account of the additional supply rail. Moreover, further disadvantages for the layout result form the use of the additional supply potential; by way of example, a well isolation is required in the layout. A further problem results from the fact that the nodes between the turned-off circuit parts and the shadow latch have a non-defined, floating potential, which would lead to high short-circuit currents into the shadow latch. For this reason, the shadow latch is normally isolated from the rest of the circuit by so-called transmission gates. The driving of the transmission gates requires two further control signals which have to be additionally fed to the flip-flop, which is associated with further outlay in the layout. In addition, these signals must also be valid in the turned-off state of the circuit block, that is to say that the gates which generate these signals have to be supplied, like the shadow latch, likewise by the supply potential that is not turned off.